Sandblaster Low-Power Multithreaded SDR Baseband Processor
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چکیده
General-purpose processors have utilized complex and energy inefficient techniques to accelerate performance. In embedded DSP designs, power constraints have precluded general-purpose microarchitectural techniques. Rather than minimize average execution time, embedded DSP processors require the worst-case execution time to be minimized. Subsequently, Very Long Instruction Word (VLIW) processors have been employed, but architecturally visible side effects have imposed restrictions on parallelism due to interrupt and latency considerations – particularly if all loads must complete prior to servicing interrupts. In this paper, we present a low-power multithreaded interlocked (transparent) processor capable of parallelizing non-associative DSP arithmetic. We describe specific memory and logic techniques for reducing power dissipation and discuss how multithreading enables low-power optimization. We further describe the programming environment for our SDR DSP processor. Finally, we present automated results for complete physical layer processing of a number of communications protocols including WCDMA, GSM/GPRS, WLAN, and GPS.
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تاریخ انتشار 2004